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AM1802 데이터시트(PDF) 39 Page - Texas Instruments

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부품명 AM1802
상세설명  AM1802 ARM Microprocessor
PDF  180 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

AM1802 데이터시트(HTML) 39 Page - Texas Instruments

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AM1802
www.ti.com
SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012
3
Device Configuration
3.1
Boot Modes
This device supports a variety of boot modes through an internal ARM ROM bootloader. This device does
not support dedicated hardware boot modes. The input states of the BOOT pins are sampled and latched
into the BOOTCFG register, which is part of the system configuration (SYSCFG) module, when device
reset is deasserted. Boot mode selection is determined by the values of the BOOT pins.
See Using the OMAP-L1x8 Bootloader Application Report (SPRAB41) for more details on the ROM Boot
Loader.
The following boot modes are supported:
•
NAND Flash boot
–
8-bit NAND
–
16-bit NAND (supported on ROM revisions after d800k002 -- see the bootloader documents
mentioned above to determine the ROM revision)
•
NOR Flash boot
–
NOR Direct boot (8-bit or 16-bit)
–
NOR Legacy boot (8-bit or 16-bit)
–
NOR AIS boot (8-bit or 16-bit)
•
I2C0 Boot
–
EEPROM (Master Mode)
–
External Host (Slave Mode)
•
SPI0/ SPI1 Boot
–
Serial Flash (Master Mode)
–
SERIAL EEPROM (Master Mode)
–
External Host (Slave Mode)
•
UART0/UART1/UART2 Boot
–
External Host
•
MMC/SD0 Boot
3.2
SYSCFG Module
The following system level features of the chip are controlled by the SYSCFG peripheral:
•
Readable Device, Die, and Chip Revision ID
•
Control of Pin Multiplexing
•
Priority of bus accesses different bus masters in the system
•
Capture at power on reset the chip BOOT pin values and make them available to software
•
Control of the DeepSleep power management function
•
Enable and selection of the programmable pin pullups and pulldowns
•
Special case settings for peripherals:
–
Locking of PLL controller settings
–
Default burst sizes for EDMA3 transfer controllers
–
McASP AMUTEIN selection and clearing of AMUTE status for the McASP
–
Control of the reference clock source and other side-band signals for both of the integrated USB
PHYs
–
Clock source selection for EMIFA
–
DDR2 Controller PHY settings
•
Selects the source of emulation suspend signal (from ARM) of peripherals supporting this function.
Copyright © 2010–2012, Texas Instruments Incorporated
Device Configuration
39
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Product Folder Link(s): AM1802



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