Analog Integrated Circuit Device Data



Freescale Semiconductor

33

33814

5.3.2

Power ON Reset (POR)

operating state. The Power On Reset circuit incorporates a timer to prevent high frequency transients from causing an erroneous

POR.

Upon enabling the device (KEYSW High), outputs will be activated based on the initial state of the control register or parallel

Figure 11. 33814 Functional State Diagram

Table 13. Operational States

KEYSW Input

PWREN SPI Bit

Input

BATSWB Output

All Supplies

STATE

L

L

L

OFF

Sleep

H

L

H

ON

NORMAL

H

H

H

ON

NORMAL

L

H

L

ON

Prepare to shutdown

SLEEP

(Engine/Key is off)

RESETB=0

BATSW=0

RESET

(Resets ASIC & MCU)

RESETB=0

BATSW=1

NORMAL

(SPI Bus Usable)

RESETB=1

BATSW=1

PREPARE TO

SHUTDOWN

(SPI Bus Usable)

RESETB=1

BATSW=0

KE

YS

W

=1

VPWR_OV=1 ||

VCC_UV=1||

VCC_POR=1

OV – Over Voltage

UV – Under Voltage

WD = Watch Dog

TD = Time Delay

POR = Power On Reset

&& = logic AND

|| = logic OR

KEY

SW

=0

VP

W

R_

OV

=0

&&

VC

C_

PO

R=

0 +

TD

=

128

uS

W

D_

TIM

EO

UT

=1 |

|

VP

W

R_

OV

=1 |

|

VC

C_

UV

=1

PWREN=1

PW

RE

N=

0

KE

YS

W

=0

&&

PW

RE

N=

1

KEYSW=0 &&

PWREN=0

VPWR_UV=1

from any state

KEYSW=0

Passive State

Active States

SPI_RESET

(Resets ASIC Only)

RESETB=1

BATSW=1

Over-voltage

Under-voltage

Watchdog