DAC5675MPHPREP datasheet(7/27 Pages) TI1

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Digital Specifications

DAC5675-EP

SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006

over operating free-air temperature range, typical values at 25

°C, AV

DD = 3.3 V, DVDD = 3.3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVDS Interface: Nodes D[13:0]A, D[13:0]B

Positive-going differential input

VITH+

100

voltage threshold

See LVDS Min/Max Threshold

Voltages table

Negative-going differential input

VITH–

–100

voltage threshold

Internal termination impedance

110

132

Ω

Input capacitance

CMOS Interface (SLEEP)

VIH

High-level input voltage

3.3

VIL

Low-level input voltage

0.8

IIH

High-level input current

–100

100

µA

IIL

Low-level input current

–10

µA

Input capacitance

Clock Interface (CLK, CLKC)

|CLK-CLKC|

Clock differential input voltage

0.4

0.8

VPP

tw(H)

Clock pulse width high

1.25

tw(L)

Clock pulse width low

1.25

Clock duty cycle

40%

60%

VCM

Common-mode voltage range

± 20%

Input resistance

Node CLK, CLKC

670

Ω

Input capacitance

Node CLK, CLKC

Input resistance

Differential

1.3

Ω

Input capacitance

Differential

Timing

tSU

Input setup time

1.5

Input hold time

0.25

tLPH

Input latch pulse high time

tDD

Digital delay time

DLL disabled, DLLOFF = 1

clk

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