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MPT57604 데이터시트(PDF) 8 Page - Texas Instruments |
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MPT57604 데이터시트(HTML) 8 Page - Texas Instruments |
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8 / 10 page ![]() MPT57604 192/200-OUTPUT TFT GATE DRIVER SGLS109 - JANUARY 2000 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over full range of recommended operating conditions, VSS = 0 V (unless otherwise noted) PARAMETER MIN MAX UNIT fCP Operating frequency 100 KHz tCPVH, tCPVL CPV clock pulse width 4 µs tWCL Clear enable time 1 µs tsu Data setup time 700 ns th Data hold time 700 ns switching characteristics over full range of recommended operating conditions, VSS = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT tpd1 Propagation delay time, CPV to outputs CL = 300 pF 1000 ns tpd2 Propagation delay time, CPV to STV2 CL = 30 pF 800 ns tpd3 Propagation delay time, output enables to outputs CL = 300 pF 1000 ns NOTE: The ac timing is 50% of the I/O amplitude, for each signal. |
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