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VSP01M02 데이터시트(PDF) 13 Page - Texas Instruments

부품명 VSP01M02
상세설명  CCD Analog Front-End with Timing Generator and Vertical Driver for Digital Cameras
PDF  91 Pages
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VSP01M02 데이터시트(HTML) 13 Page - Texas Instruments

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SLAVE MODE: VD, HD SPECIFICATIONS
VD, HD Detect
VD
MCK
VDAfterHD
HD
HDAfterVD
HD
t
ODDHD-VD
t
ODDVD-HD
t
HD
t
VD
VD
MCK
VDAfterHD
HD
HDAfterVD
HD
t
ODDHD-VD
t
ODDVD-HD
VSP01M01
VSP01M02
www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009
The odd field of the two-field CCD operation and the first field of the even field operation is detected by the VD
and HD phase. The delay limit of the VD and HD phase is specified in Figure 2 and Figure 3.
Figure 2. VD, HD Falling Edge Detect
Figure 3. VD, HD Rising Edge Detect
Table 3. Timing Characteristics for Figure 2 and Figure 3(1)
PARAMETER
MIN
TYP
MAX
UNIT
tVD
VD trail-to-trail
10
τ (MCK cycles)
tHD
HD trail-to-trail
10
τ (MCK cycles)
VD trail delay limit for ODD detect
tODD HD-VD
0
1
6
τ (MCK cycles)
(register setting 02Fh[2:0])
HD trail delay limit for ODD detect
tODD HD-VD
0
1
6
τ (MCK cycles)
(register setting 02Fh[5:3])
(1)
The VD, HD edge is detected by the rising edge of MCK.
Copyright © 2009, Texas Instruments Incorporated
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