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Board Layout

3

Board Layout

This section provides a description of the TPS54519EVM-037, board layout, and layer illustrations.

3.1

Layout

Figure 13 through Figure 17 shows the board layout for the TPS54519EVM-037. The top-side layer of the

EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz.

copper.

The top layer contains the main power traces for V

connections for the remaining pins of the TPS54519 and a large area filled with ground. The bottom and

internal layers contain ground planes only. The top-side ground areas are connected to the bottom and

internal ground planes with multiple vias placed around the board including four vias directly under the

TPS54519 device to provide a thermal path from the top-side ground area to the bottom-side and internal

ground planes.

The input decoupling capacitors (C2 and C3) and bootstrap capacitor (C6) are all located as close to the

IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC.

The voltage divider network ties to the output voltage at the point of regulation, the copper V

the output connector J4. For the TPS54519, an additional input bulk capacitor may be required, depending

on the EVM connection to the input supply.

Figure 13. TPS54519EVM-037 Top-Side Layout

11

SLVU523

– September 2011

TPS54519EVM-037, 5-A, SWIFT

™ Regulator— Evaluation Module

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