CPC5002GSTR datasheet(5/14 Pages) IXYS

5 / 14 page

INTEGRATED CIRCUITS DIVISION

CPC5002

R01

www.ixysic.com

1.9 Switching Specifications

1 Falling propagation delay can be reduced by increasing instantaneous LED current drive, typically by increasing C

FWD .

2 Rising propagation delay depends on R

PU , CL , and IF .

Increasing IF above 2 • ITH (by reducing RS) increases the rising propagation delay.

3 Propagation Delay Skew is the worst case difference propagation delay, High to Low and Low to High between the two channels of a CPC5002

when measured using the test circuit shown below, which is tuned for approximately even rising and falling delays.

1.10 Propagation Delay Test Circuit

Parameter

Conditions

Symbol

Min

Typ

Max

Units

Timing Specifications

Clock Frequency

ISINK=6mA, CL=20pF

fMAX

-10-

MHz

Propagation Delay

Output Falling 1, 3

IF=1.5mA, VDD=3.3V,

RPU=499, CL=20pF,

0.5VIN to 0.5VDD_OUT

tPHL

120

Output Rising 2, 3

tPLH

120

Pulse Width Distortion: |tPLH - tPLH|

As per tPHL and tPLH

PWD

Propagation Delay Skew 3

As per tPHL and tPLH

tPSK

Output Fall Time, 90% to 10%

IF=1.5mA, VDD=3.3V,

RPU=499, CL=20pF

Common Mode Specifications

Common Mode Transient Immunity

VCM=20VP-P , VDD=3.3V, TA=25°C

VOUT = High

VOUT>2V

CMH

kV/

s

VOUT = Low

VOUT<0.8V

CML

27pF

3.3V

499

20pF

OUT

½ CPC5002

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