전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

XTNETA1622DW 데이터시트(PDF) 10 Page - Texas Instruments

부품명 XTNETA1622DW
상세설명  ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

XTNETA1622DW 데이터시트(HTML) 10 Page - Texas Instruments

Back Button XTNETA1622DW Datasheet HTML 6Page - Texas Instruments XTNETA1622DW Datasheet HTML 7Page - Texas Instruments XTNETA1622DW Datasheet HTML 8Page - Texas Instruments XTNETA1622DW Datasheet HTML 9Page - Texas Instruments XTNETA1622DW Datasheet HTML 10Page - Texas Instruments XTNETA1622DW Datasheet HTML 11Page - Texas Instruments XTNETA1622DW Datasheet HTML 12Page - Texas Instruments XTNETA1622DW Datasheet HTML 13Page - Texas Instruments XTNETA1622DW Datasheet HTML 14Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 68 page
background image
TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64BIT PCIHOST INTERFACE
SDNS033B − JUNE 1995 − REVISED MAY 1996
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
timing requirements (see Note 4 and Figure 1)
NO.
MIN
MAX
UNIT
1
tw(RESCLKH)
Pulse duration, RESCLK high
12
ns
2
tw(RESCLKL)
Pulse duration, RESCLK low
12
ns
3
tsu(RESSOC)
Setup time, RESSOC high before RESCLK
↑
10
ns
4
tsu(RESEN)
Setup time, RESEN low before RESCLK
↑
10
ns
5
tsu(RESDATA)
Setup time, RESDATA7 − RESDATA0 valid before RESCLK
↑
10
ns
6
tsu(RESPAR)
Setup time, RESPAR valid before RESCLK
↑
10
ns
7
th(RESSOC)
Hold time, RESSOC high after RESCLK
↑
1
ns
8
th(RESEN)
Hold time, RESEN low after RESCLK
↑
1
ns
NOTE 4: All output signals are generated on the rising edge of RESCLK.
operating characteristics (see Note 4 and Figure 1)
NO.
MIN
MAX
UNIT
9
td(RESCLAV)
Delay time, RESCLK
↑ to RESCLAV↑
1
20
ns
10
td(RESPERR)1
Delay time, RESCLK
↑ to RESPERR↓
1
20
ns
11
td(RESPERR)2
Delay time, RESCLK
↑ to RESPERR↑
1
20
ns
NOTE 4: All output signals are generated on the rising edge of RESCLK.
RESDATA7 −
RESDATA0
(input)
RESCLAV
(output)
RESCLK
(input)
1
2
RESSOC
(input)
9
7
RESEN
(input)
8
Byte 53
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
3
4
5
Parity
Error
No Parity Error
11
6
10
RESPAR
(input)
RESPERR
(output)
Figure 1. Reassembly-Cell Interface (PHY/ATM Low)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com