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TNETX3270 데이터시트(PDF) 61 Page - Texas Instruments

부품명 TNETX3270
상세설명  ThunderSWITCHE 24/3 ETHERNETE SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
PDF  66 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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TNETX3270 데이터시트(HTML) 61 Page - Texas Instruments

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TNETX3270
ThunderSWITCH
™ 24/3 ETHERNET™ SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999
61
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
EEPROM interface
operating characteristics over recommended operating conditions (see Figure 21)
NO
PARAMETER
TNETX3150
TNETX3150A
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
fclock (ECLK)
Clock frequency, ECLK
98
98
kHz
1
td (ECLKH–EDIOL)
Delay time, from ECLK
↑ to EDIO↓ (see Note 9)
5
5
µs
2
td (EDIOL–ECLKL)
Delay time, from EDIO
↓ to ECLK↓ (see Note 9)
5
5
µs
3
td (ECLKL–EDIOX)
Delay time, from ECLK
↓ to EDIO changing (see Note 10)
0
0
µs
4
td (EDIOV–ECLKH)
Delay time, from EDIO valid output to ECLK
↑
0
0
µs
5
td (ECLKL–EDIOV)
Delay time, from ECLK
↓ to EDIO valid
0
0
µs
6
td (ECLKL–EDIOX)
Delay time, from ECLK
↓ to EDIO changing (see Note 11)
0
0
µs
7
td (ECLKH–EDIOX)
Delay time, from ECLK
↑ to EDIO invalid
5
5
µs
8
td (EDIOV–ECLKH)
Delay time, from EDIO valid input to ECLK
↑
10
10
µs
NOTES:
9. This is a start condition delay time during ECLK high.
10. This is a changing-data condition delay time for output EDIO.
11. This is a changing-data condition delay time for input EDIO.
7
ECLK
(output)
EDIO
(output)
EDIO
(input)
1
6
4
8
Valid
Valid
Valid
Valid
5
23
Figure 21. EEPROM



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