TNETX3270PGV datasheet(52/66 Pages) TI1

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TNETX3270

ThunderSWITCH

™ 24/3 ETHERNET™ SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Outputs are driven to a minimum high-logic level of 3.3 V and to a maximum low-logic level of 0 V.

Output transition times are specified as follows: For a high-to-low transition on either an input or output signal, the

level at which the signal is said to be no longer high is 1.4 V and the level at which the signal is said to be low is 1.4 V.

For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level at which

the signal is said to be high is 2 V, as shown in the following.

The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically

1.5 ns.

0.8 V (low)

2 V (high)

1.4 V

test measurement

The test-and-load circuit shown in Figure 12 represents the programmable load of the tester pin that is used

to verify timing parameters of the TNETX3270 output signals.

TTL OUTPUT TEST LOAD

IOH

VLOAD

IOL

Where: IOL

= Refer to IOL in recommended operating conditions.

IOH

= Refer to IOH in recommended operating conditions.

VLOAD = 1.5 V, typical dc-level verification or

1.5 V, typical timing verification

= 45 pF, typical load-circuit capacitance

TTL

Output

Under

Test

Point

Figure 12. Test-and-Load Circuit

TNETX3270PGV 데이터시트(PDF) 52 Page - Texas Instruments