TNETX4090 datasheet(66/78 Pages) TI1

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TNETX4090

ThunderSWITCH II™ 9-PORT 100-/1000-MBIT/S ETHERNET™ SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

MII (ports 0–8)

Figures 21–23 show the timing for the eight MIIs operating at either 10-Mbit/s or 100-Mbit/s, and the GMII

operating at 100-Mbit/s.

Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_RXD3–Mxx_RXD0 is driven by the PHY

on the falling edge of Mxx_RCLK. Mxx_RXD3–Mxx_RXD0 timing must be met during clock periods in which

Mxx_RXDV is asserted. Mxx_RXDV is asserted and deasserted by the PHY on the falling edge of Mxx_RCLK.

Mxx_RXER is driven by the PHY on the falling edge of Mxx_RCLK.

MII receive (see Figure 21)

NO.

MIN

MAX

UNIT

tsu(Mxx_RXD)

Setup time, Mxx_RXD3–Mxx_RXD0 valid before Mxx_RCLK

↑

tsu(Mxx_RXDV) Setup time, Mxx_RXDV valid before Mxx_RCLK↑

tsu(Mxx_RXER) Setup time, Mxx_RXER valid before Mxx_RCLK↑

th(Mxx_RXD)

Hold time, Mxx_RXD3–Mxx_RXD0 valid after Mxx_RCLK

↑

th(Mxx_RXDV)

Hold time, Mxx_RXDV valid after Mxx_RCLK

↑

th(Mxx_RXER)

Hold time, Mxx_RXER valid after Mxx_RCLK

↑

Mxx_RXD3–Mxx_RXD0

Mxx_RXDV

Mxx_RXER

Mxx_RCLK

Figure 21. MII Receive

NOTE: For port 8, M08_RFCLK is used for the transmit clock input.

Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_TXD3–Mxx_TXD0 is driven by the

reconciliation sublayer synchronous to Mxx_TCLK. Mxx_TXEN is asserted and deasserted by the reconciliation

sublayer synchronous to the Mxx_TCLK rising edge. Mxx_TXER is driven synchronous to the rising edge of

Mxx_TCLK.

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