KMB-001CEVALZ datasheet(13/34 Pages) INTERSIL

13 / 34 page

ISLA214P12

FN7982.2

June 27, 2012

FIGURE 2B. CMOS SDR

FIGURE 2. CMOS TIMING DIAGRAMS

Timing Diagrams (Continued)

CLKN

CLKP

INP

INN

CLKOUT

tCPD

D[13:0]

LATENCY = L CYCLES

tDC

tPD

DATA

N-L

DATA

N-L+1

DATA

Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.

PARAMETER

SYMBOL

CONDITION

MIN

(Note 5)

TYP

MAX

(Note 5)

UNITS

ADC OUTPUT

Aperture Delay

114

RMS Aperture Jitter

Input Clock to Output Clock Propagation

Delay

tCPD

AVDD, OVDD = 1.7V to 1.9V,

TA = -40°C to +85°C

1.65

2.4

tCPD

AVDD, OVDD = 1.8V, TA = +25°C

1.9

2.3

2.75

Relative Input Clock to Output Clock

Propagation Delay (Note 12)

dtCPD

AVDD, OVDD = 1.7V to 1.9V,

TA = -40°C to +85°C

-450

450

Input Clock to Data Propagation Delay

tPD

1.65

2.4

3.5

Output Clock to Data Propagation Delay,

LVDS Mode

tDC

Rising/Falling Edge

-0.1

0.16

0.5

Output Clock to Data Propagation Delay,

CMOS Mode

tDC

Rising/Falling Edge

-0.1

0.2

0.65

Synchronous Clock Divider Reset Setup

Time (with respect to the positive edge of

CLKP)

tRSTS

0.4

0.06

Synchronous Clock Divider Reset Hold Time

(with respect to the positive edge of CLKP)

tRSTH

0.02

0.35

Synchronous Clock Divider Reset Recovery

Time

tRSTRT

DLL recovery time after

Synchronous Reset

(sample clock not interrupted)

cycles

Latency (Pipeline Delay)

cycles

Overvoltage Recovery

tOVR

1cycles

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