12

Preliminary Specification

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

©2001 Silicon Storage Technology, Inc.

S71147-02-000

5/01

398

398 ILL F07.1

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note

Note: Toggle bit output is always high first.

AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

398 ILL F08.1

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10)

SAX = Sector Address

AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

ADDRESS AMS-0

DQ7-0

WE#

SW0

SW1

SW2

SW3

SW4

SW5

5555

2AAA

2AAA

5555

5555

55

30

55

AA

80

AA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP