SST45VF010 datasheet(2/16 Pages) SST

2 / 16 page

S71178

514-1 10/00

512 Kbit / 1 Mbit / 2 Mbit Serial Flash

SST45VF512 / SST45VF010 / SST45VF020

Advance Information

FUNCTIONAL BLOCK DIAGRAM

Reset

Reset will terminate any operation, e.g., Read, Erase

and Program, in progress. It is activated by a high to low

transition on the RESET# pin. The device will remain in

reset condition as long as RESET# is low. Minimum reset

time is 10µs. See Figure 14 for reset timing diagram.

RESET# is internally pulled-up and could remain uncon-

nected during normal operation. After reset, the device is

in standby mode, a high to low transition on CE# is

required to start the next operation.

An internal power-on reset circuit protects against acci-

dental data writes. Applying a logic level low to RESET#

during the power-on process then changing to a logic

level high when VDD has reached the correct voltage

level will provide additional protection against accidental

writes during power on.

Read SST ID/Read Device ID

The Read SST ID and Read Device ID operations read

the JEDEC assigned manufacturer identification and the

manufacturer assigned device identification codes.

These codes may be used to determine the actual device

resident in the system.

Write Protect

The WP# pin provides inadvertent write protection. The

WP# pin must be held high for any Erase or Program

operation. The WP# pin is “don’t care” for all other

operations. In typical use, the WP# pin is connected to

VSS with a standard pull-down resistor. WP# is then

driven high whenever an Erase or Program operation is

required. If the WP# pin is tied to VDD with a pull-up

resistor, then all operations may occur and the write

protection feature is disabled. The WP# pin has an

internal pull-up and could remain unconnected when not

used.

514ILL B1.0

I/O Buffers

and

Data Latches

SuperFlash

Cell Array

X - Decoder

Control Logic

Address

Buffers

and

Latches

CE#

Y - Decoder

SCK

WP# RESET#

Serial Interface

TABLE 1: PRODUCT IDENTIFICATION

Byte

Data

Manufacturer’s ID

0000 H

BF H

Device ID

SST45VF512

0001 H

41 H

SST45VF010

0001 H

45 H

SST45VF020

0001 H

43 H

514 PGM T1.4

SST45VF010 데이터시트(PDF) 2 Page - Silicon Storage Technology, Inc

SST45VF010 데이터시트(HTML) 2 Page - Silicon Storage Technology, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

데이터시트 다운로드

링크 URL