16

Advance Information

4 Mbit LPC Flash

SST49LF040

©2001 Silicon Storage Technology, Inc.

S71213-00-000

11/01 562

TABLE

Mode

RST#

OE#

WE#

DQ

Address

Read

Program

Erase

Sector or Block address,

XXH for Chip-Erase

Reset

XX

High Z

X

Write Inhibit

X

XX

X

Product Identification

Manufacturer’s ID (BFH)

See Table 8

T7.2 562

2. Device ID 51H for SST49LF040

TABLE

Command

Sequence

Cycle

1. LPC mode uses consecutive Write cycles to complete a command sequence; PP mode uses consecutive bus cycles to complete a

command sequence.

2nd1

Cycle

3rd1

Cycle

4th1

Cycle

5th1

Cycle

6th1

Cycle

2. YYYY = A[31:16]

In LPC mode, during SDP command sequence, YYYY must be within memory address range specified in Figures 4 and 5.

Data

Addr2

Data

Addr2

Data

Addr2

Data

Addr2

Data

Addr2

Data

Byte-

Program

YYYY 5555H

AAH

YYYY 2AAAH

55H

YYYY 5555H

A0H

3. PA = Program Byte address

Data

Sector-

Erase

YYYY 5555H

AAH

YYYY 2AAAH

55H

YYYY 5555H

80H

YYYY 5555H

AAH

YYYY 2AAAH

55H

4. SAx for Sector-Erase Address

30H

Block-Erase

YYYY 5555H

AAH

YYYY 2AAAH

55H

YYYY 5555H

80H

YYYY 5555H

AAH

YYYY 2AAAH

55H

5. BAx for Block-Erase Address

50H

6. Chip-Erase is supported in PP mode only

YYYY 5555H

AAH

YYYY 2AAAH

55H

YYYY 5555H

80H

YYYY 5555H

AAH

YYYY 2AAAH

55H

YYYY 5555H

10H

Software

ID Entry

YYYY 5555H

AAH

YYYY 2AAAH

55H

YYYY 5555H

90H

Software

8. Both Software ID Exit operations are equivalent

XXXX XXXXH

F0H

Software

ID Exit8

YYYY 5555H

AAH

YYYY 2AAAH

55H

YYYY 5555H

F0H

T8.3 562