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UVLO

Thermal

Shutdown

Shutdown

2.5V

+

-

Current

Sense

Reference

V

ref

V

ref

ENA_1

10kW

RisingEdge

Deglitch

0.95

V

FB2

FallingEdge

Delay

V

IN1

0.95

V

FB1

RisingEdge

Deglitch

FallingEdge

Deglitch

FB2

UVComp

FallingEdge

Deglitch

FB1

UVComp

Power

Sequence

Logic

Shutdown

ENA_1

ENA_2

V

IN1

Current

Sense

+

-

10kW

ENA_2

ENA_2

FB2

V

ref

V

(2Pins)

IN1

GND

EN

SEQ

(seeNoteB)

V

(2Pins)

IN2

V

(2Pins)

OUT1

V

SENSE1

(seeNote A)

PG1

MR2

RESET

MR1

V

SENSE2

(seeNote A)

V

(2Pins)

OUT2

FB1

V

IN1

ENA_1

0.83

V

0.83

V

NOTES: A. Formostapplications,VSENSE1 andVSENSE2 shouldbeexternallyconnectedtoVOUT ascloseaspossibletothedevice.

Forotherimplementations,refertotheSENSEterminalconnectiondiscussioninthe ApplicationInformationsection.

B. IftheSEQterminalisfloatingattheinput,VOUT2 powersupfirst.

TPS70751-EP

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR

WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS

SLVS718 – DECEMBER 2006

DETAILED BLOCK DIAGRAM – FIXED-VOLTAGE VERSION

3

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