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SN74ALVC00-EP 데이터시트(PDF) 1 Page - Texas Instruments |
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SN74ALVC00-EP 데이터시트(HTML) 1 Page - Texas Instruments |
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1 / 9 page ![]() SN74ALVC00EP QUADRUPLE 2INPUT POSITIVENAND GATE SCES521A − DECEMBER 2003 − REVISED MAY 2004 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Controlled Baseline − One Assembly/Test Site, One Fabrication Site D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. D Operates From 1.65 V to 3.6 V D Max tpd of 3 ns at 3.3 V D ±24-mA Output Drive at 3.3 V D Latch-Up Performance Exceeds 250 mA Per JESD 17 description/ordering informatiom The SN74ALVC00 quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation. The device performs the Boolean function Y = A • B or Y = A + B in positive logic. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40 °C to 85°C SOIC − D Tape and reel SN74ALVC00IDREP ALVC00IEP −40 °C to 85°C TSSOP − PW Tape and reel SN74ALVC00IPWREP§ ALVC00E ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. § Product Preview FUNCTION TABLE (each gate) INPUTS OUTPUT A B OUTPUT Y H H L L XH X L H logic diagram, each gate (positive logic) A B Y Copyright 2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 1B 1Y 2A 2B 2Y GND VCC 4B 4A 4Y 3B 3A 3Y |
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