SL3ICS1202 datasheet(29/56 Pages) NXP

29 / 56 page

139036

All information provided in this document is subject to legal disclaimers.

Product data sheet

COMPANY PUBLIC

Rev. 3.6 — 10 March 2011

139036

29 of 56

NXP Semiconductors

SL3ICS1002/1202

UCODE G2XM and G2XL

15.1 G2X Memory

For the general memory layout according to the standard Section 18, Ref. 1, refer to

Figure 6.17. The tag memory is logically subdivided into four distinct banks.

In accordance to the standard Section 18, Ref. 1, section 6.3.2.1. The tag memory of the

SL3ICS1002 G2XM is organized in following 4 memory sections:

The logical address of all memory banks begin at zero (00h).

Table 15.

G2X memory sections

Name

Size

Bank

Reserved memory (32 bit ACCESS and 32 bit KILL password)

64 bit

00b

EPC (excluding 16 bit CRC-16 and 16 bit PC)

240 bit

01b

TID (including unique 32 bit serial number)

64 bit

10b

User memory (G2XM only)

512 bit

11b

Fig 9.

G2X TID memory structure

Class Identifier

Mask-Designer Identifier

Model Number

Serial Number

TID

00h

07h

08h

13h

14h

1Fh

20h

3Fh

14h

1Fh

18h

19h

Version Number

Sub Version Number

E2h

006h

00000001h to FFFFFFFFh

Whenever the 32 bit serial

is exceeded the sub version

is incremented by 1

3Fh

00h

Addresses

Bits

LS Byte

LSBit

MSBit

MS Byte

LSBit

MSBit

00000b

0000010b

Sub Version Nr

Version (Silicon) Nr

Model Nr.

Mask ID

UCode EPC G2XM

00000b

0000011b

003h

006h

UCode EPC G2XL

00000b

0000100b

004h

006h

002h

SL3ICS1202 데이터시트(PDF) 29 Page - NXP Semiconductors

SL3ICS1202 데이터시트(HTML) 29 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

데이터시트 다운로드

링크 URL