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TNETA1500APGE 데이터시트(PDF) 3 Page - Texas Instruments |
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TNETA1500APGE 데이터시트(HTML) 3 Page - Texas Instruments |
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3 / 10 page ![]() TNETA1500A 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER SDNS042A – AUGUST 1997 – REVISED JANUARY 1998 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram TD0–TD7 A0–A7 Clock Recovery Framing and Serial-to-Parallel Conversion Descrambling, B1-Parity, Alarm Generation Demux ATM-Cell Extraction and Descrambling Controller Interface ATM-Cell Scrambling and Cell Insertion RD0–RD7 RCKI RXCELL RRE RXFE RSDT RSDC CKRECBP Mux D0–D7 READY RD/WR INTR SEL TCKI TXCELL TWE TXAF Scrambling and B1-Parity Generation Parallel-to-Serial Conversion CLKLOOP TSDC TSCT Clock Generation CKGENBP TXREFCK TXHCKT LOF FLB OOF B1ERR LAIS LOSRD LOCA LFERF TLB 8 8 8 8 TSCC TSDT FLAGT FLAGC TXHCKC RSCT RSCC RESET CRCAP LOS LOP OE CGCAP 0.01- µF Capacitor Connected Externally SDHENABLE 330-pF Capacitor Connected Externally Receive Operation Transmit Operation 8KHZREF |
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