ThunderLAN

™ TNETE100A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996

19

POST OFFICE BOX 1443

MIN

MAX

UNIT

tsu(MRX pins)

Setup time, MRXD[3:0], MRXDV, MRXER (see Note 20)

10

ns

th(MRX pins)

Hold time, MRXD[3:0], MRXDV, MRXER (see Note 20)

10

ns

PARAMETER

MIN

MAX

UNIT

td(MTX pins)

Delay time, MTCLK to MTXD[3:0], MTXEN, and MTXER outputs (see Note 21)

0

25

ns

† Both MCRS and MCOL are driven asynchronously by the PHY.

NOTES: 20. MRXD[3:0] is driven by the PHY on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the edge

of MRCLK. MRXD[3:0] timing must be met during clock periods where MRXDV is asserted. MRXDV is asserted and deasserted

by the PHY on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the rising edge of MRCLK.

MRXER is driven by the PHY on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the rising

edge of MRCLK. MRXER timing must be met during clock periods when MRXDV is asserted.

21. MTXD[3:0] is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted and deasserted by the

reconciliation sublayer synchronous to the MTCLK rising edge. MTXER is driven synchronous to the rising edge of MTCLK.

td(MTX pins)

MTCLK

MTXD[3:0],

MTXEN,

MTXER

tsu(MRX pins)

th(MRX pins)

MRCLK

MRXD[3:0],

MRXDV,

MRXER

Figure 5. MII Transmit and Receive Timing