ThunderLAN

™ TNETE110A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996

8

POST OFFICE BOX 1443

Pin Functions (Continued)

PIN

TYPE†

DESCRIPTION

NAME

NO.

TYPE†

DESCRIPTION

NETWORK INTERFACE (10 Base-T AND AUI) (CONTINUED)

FXMTP

FXMTN

97

98

A

10 Base-T transmit pair. FXMTP and FXMTN are differential line transmitter outputs.

RESERVED

120

I

Reserved. Tie this pin low.

SERIAL MANAGEMENT INTERFACE

MDIO

93

I/O

Management data I/O. MDIO is part of the serial management interface.

MDCLK

91

O

Management data clock. MDCLK is part of the serial management interface to physical-media

independent (PMI)/PHY chip.

MRST

95

O

MII reset. MRST is the reset signal.

POWER

VDDI

6, 14,

34, 48,

122,

136,

142

PWR

PCI VDD pins. VDDI pins provide power for the PCI I/O pin drivers. Connect VDDI pins to a 5-V power

supply when using 5-V signals on the PCI bus. Connect VDDI pins to a 3-volt power supply when using

3-V signals on the PCI bus.

VDDL

22, 37,

58, 70,

79, 84

94,

130

PWR

Logic VDD pins (5 V). VDDL pins provide power for internal TNETE110A logic, and they should always

be connected to 5 V.

VDDOSC

115

PWR

Analog power pin. VDDOSC is the 5-V power for the crystal oscillator circuit.

VDDR

104

107

PWR

Analog power pin. VDDR is the 5-V power for the receiver circuitry.

VDDT

96

PWR

Analog power pin. VDDT is the 5-V power for the transmitter circuitry.

VDDVCO

117

PWR

Analog power pin. VDDVCO is the 5-V power for the voltage controller oscillator (VCO) and filter input.

VSSI

3, 10,

26, 31,

40, 52,

67, 88,

127,

139

PWR

PCI I / O ground pins

VSSL

18, 44,

63, 75,

92,

133

PWR

Logic ground pins

VSSOSC

112

PWR

Analog power pin. Ground for crystal oscillator circuit

VSSR

102

110

PWR

Analog power pin. Ground for receiver circuitry

VSST

101

PWR

Analog power pin. Ground for transmitter circuitry

VSSVCO

119

PWR

Analog power pin. Ground for VCO and filter input

† I = input, A = analog, PWR = power

architecture

The major blocks of the TNETE110A include the PCI interface (PCIIF), protocol handler (PH), physical layer

(PHY), FIFO pointer registers (FPREGS), FIFO SRAM (FSRAM), and a test-access port (TAP). The

functionality of these blocks is described in the following sections.