SC5014

29

Device Control Register

Bit Field

Definition

Read / Write Description

0x0 [7:6]

WIN[:0]

R/W

A modified duty cycle sent into the PWMI pin replaces the existing saved duty cycle when its

deviation from the saved duty is outside the window for two consecutive samples.

00 = 0 bits (no window)

0 = ± bit window

0 = ±2 bit window

 = ±3 bit window

0x0 [5]

FAST_FREQ

R/W

Determines the LED PWM dimming frequency selection:

 = High PWM dimming frequency mode assuming 9-bit PWM duty cycle dimming, dividing

the system clock 0MHz / (52 x (FREQ+)).

0 = Low PWM dimming frequency mode assuming 0-bit PWM duty cycle dimming, dividing

the system clock 0MHz / (024 x (FREQ+)).

0x0 [4]

FLT_EN

R/W

This bit enables fault checking:

0 = LED_OPEN and LED_SHORT faults are not checked.

 = LED_OPEN and LED_SHORT faults are checked.

0x0 [2]

PH_SHIFT

R/W

Enables String-by-String phase shifting. This is a don’t care if INT_PWM=0.

0 = Phase shifting disabled.

 = Phase shifting is enabled.

0x0 []

INT_DUTY

R/W

Determines the duty cycle source. This is a don’t care if INT_PWM = 0.

0 = LED duty cycle is set by the PWMI input.

 = LED duty cycle is set by the 0-bit duty cycle control registers.

0x0 [0]

INT_PWM

R/W

Sets the LED PWM dimming source.

0 = LED PWM dimming driven directly from the PWMI input source (direct PWM dimming).

 = LED PWM dimming driven from an internal oscillator (required for phase-shifted PWM

dimming); enables the PLL.

Analog Dimming Control Register

Bit Field

Definition

Read / Write Description

0x02 [4:0]

IDAC [4:0]

R / W

5-bit analog dimming register — The LED current can adjusted in 32 steps from 0mA to max

value determined by R

Definition of Registers and Bits (continued)