12

Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

05/14/2012

IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,

IS64WV3216DBLL/DBLS

-8

-10

-12

Symbol

Parameter

Min. Max.

Min. Max.

Min. Max.

Unit

WriteCycleTime

8

—

10

—

12

—

ns

CE

toWriteEnd

6.5

—

8

—

9

—

ns

AddressSetupTime

6.5

—

8

—

9

—

ns

toWriteEnd

AddressHoldfromWriteEnd

0

—

0

—

0

—

ns

AddressSetupTime

0

—

0

—

0

—

ns

LB

,UBValidtoEndofWrite

6.5

—

8

—

9

—

ns

WE

PulseWidth

6.5

—

8

—

9

—

ns

WE

PulseWidth(OE=LOW)

8.0

—

10

—

11

—

ns

DataSetuptoWriteEnd

5

—

6

—

9

—

ns

DataHoldfromWriteEnd

0

—

0

—

0

—

ns

WE

LOWtoHigh-ZOutput

—

3.5

—

5

—

6

ns

WE

HIGHtoLow-ZOutput

2

—

2

—

3

—

ns

Notes:

1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0Vto3.0V

andoutputloadingspecifiedinFigure1.

2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.

3. TheinternalwritetimeisdefinedbytheoverlapofCELOWandUBorLB,andWELOW.Allsignalsmustbeinvalidstates

toinitiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedto

therisingorfallingedgeofthesignalthatterminatesthewrite.Shadedareaproductindevelopment