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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IS63WV1288DALL/DALS 데이터시트(PDF) 10 Page - Integrated Silicon Solution, Inc |
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IS63WV1288DALL/DALS 데이터시트(HTML) 10 Page - Integrated Silicon Solution, Inc |
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10 / 20 page  10 Integrated Silicon Solution, Inc. — www.issi.com Rev. B 12/15/2011 IS63WV1288DALL/DALS IS63WV1288DBLL/DBLS IS64WV1288DBLL/DBLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (OverOperatingRange) -8 ns -10 ns -12 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit twc WriteCycleTime 8 — 10 — 12 — ns tsce CE toWriteEnd 7 — 7 — 8 — ns tAw AddressSetupTimeto 8 — 8 — 8 — ns WriteEnd thA AddressHoldfrom 0 — 0 — 0 — ns WriteEnd tsA AddressSetupTime 0 — 0 — 0 — ns tPwe 1 (1) WE PulseWidth(OE High) 7 — 7 — 8 — ns tPwe 2 (2) WE PulseWidth(OE Low) 8 — 10 — 12 — ns tsd DataSetuptoWriteEnd 5 — 5 — 6 — ns thd DataHoldfromWriteEnd 0 — 0 — 0 — ns thzwe(2) WE LOWtoHigh-ZOutput — 4 — 5 — 6 ns tlzwe(2) WE HIGHtoLow-ZOutput 3 — 3 — 3 — ns Notes: 1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0to3.0Vand outputloadingspecifiedinFigure1. 2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested. 3. TheinternalwritetimeisdefinedbytheoverlapofCELOWandWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite, butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfalling edgeofthesignalthatterminatestheWrite. WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (OverOperatingRange) -20 ns -25 ns -35 ns -45ns Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit twc WriteCycleTime 20— 25— 35— 45— ns tsce CE toWriteEnd 12— 18— 25— 35— ns tAw AddressSetupTime 12— 15— 25— 35— ns toWriteEnd thA AddressHoldfromWriteEnd0— 0— 0— 0— ns tsA AddressSetupTime 0— 0— 0— 0— ns tPwe1 WE PulseWidth(OE=HIGH)12— 18— 30— 35— ns tPwe2 WE PulseWidth(OE=LOW)17— 20— 30— 35— ns tsd DataSetuptoWriteEnd 9— 12— 15— 20— ns thd DataHoldfromWriteEnd 0— 0— 0— 0— ns thzwe(3) WELOWtoHigh-ZOutput —9 —12 —20 —20 ns tlzwe(3) WEHIGHtoLow-ZOutput 3— 5— 5— 5— ns Notes: 1. TestconditionsforIS61WV6416LLassumesignaltransitiontimesof1.5nsorless,timingreferencelevelsof1.25V,inputpulse levelsof0.4VtoVdd-0.3VandoutputloadingspecifiedinFigure1a. 2. TestedwiththeloadinFigure1b.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested. 3. TheinternalwritetimeisdefinedbytheoverlapofCELOWandUBorLB,andWELOW.Allsignalsmustbeinvalidstatesto initiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtothe risingorfallingedgeofthesignalthatterminatesthewrite. |
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