CXD3003R datasheet(45/137 Pages) SONY

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CXD3003R

Description of peak meter mode (see Timing Chart 1-5.)

• When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the

left or right channel.

The 96-bit clock must be input to SQCK to read out this data.

• When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is set in the LSI internal

In other words, the PCM maximum value detection register is not reset by the readout.

• To reset the PCM maximum value register to zero, set PCT1 = PCT2 = 0 or set the $AX mute.

• The Sub Q absolute time is automatically controlled in this mode.

In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in

the memory. Normal operation is conducted for the relative time.

• The final bit (L/R flag) of the 96-bit data is normally 0.

• The pre-value hold and average value interpolation data are fixed to level (–

∞) in this mode.

SENS output switching

• This command enables the SQSO pin signal to be output from the SENS pin.

When SOC2 = 0, SENS output is performed as usual.

When SOC2 = 1, the SQSO pin signal is output from the SENS pin.

At this time, the readout clock is input to the SCLK pin.

Note) SOC2 should be switched when SQCK = SCLK = high.

Command bit

DADS = 0

DADS = 1

Set to 0 when crystal = 33.8688MHz.

Set to 1 when crystal = 16.9344MHz.

Processing

Command bit

SOC2 = 0

SOC2 = 1

The SENS signal is output from the

SENS pin as usual.

The SQSO pin signal is output from the

SENS pin.

Processing

CXD3003R 데이터시트(PDF) 45 Page - Sony Corporation