Obsolete

Product(s)

- Obsolete

Product(s)

STA020

6/14

formation from it, and transmit it as user data.

The master clock , MCK, controls timing for the entire chip and must be 128xFs. As an example, if stereo

data is input to the STA020D at 44.1kHz, MCK input must be 128 times that or 5.6448MHz.

Audio Serial Port

The audio serial port is used to enter audio data and consists of three pins: SCK, SDATA and FSYNC,

SCK clocks in SDATA, which is double buffered, while FSYNC delineates the audio samples and may in-

dicate the particular channel, left or right. To support many different interfaces, M2, M1 and M0 select one

of seven different formats for the serial port. The coding is shown in Table 3 while the formats are shown

in Figure 3.

Format 0 and 1 are designed to interface with Crystal ADCs. Format 2 communicates with Motorola and

TI DSPs. Format 3 is reserved. Format 4 is compatible with the I2S standard. Formats 5 and 6 make the

STA020D look similar to existing 16- and 18-bit DACs and interpolation filters. Format 7 is an MSB-last

format and is conducive to serial arithmetic. SCK and FSYNC are outputs in Format 0 and inputs in all

other formats. In Format 2, the rising edge of FSYNC delineates samples and the falling edge must occur

a minimum of one bit period before or after the rising edge. In all formats except 2, FSYNC contains left/

right information requiring both edges of FSYNC to delineate samples. Formats 5 and 6 require a minimum

of 16- or 18-bit audio words respectively. In all formats other than 5 and 6, the STA020D can accept any

word length from 16 to 24 bits by adding leading zeros in format 7 and trailing zeros in the other formats,

or by restricting the number of SCK periods between active edges of FSYNC to the sample word length.

FSYNC must be derived from MCK, either through a DSP using the same clock or using counters. If

SFYNC moves (jitters) with respect to MCK by four MCK periods, the internal counters and CBL may be

reset.

Table 1. Audio Port Modes

M2

M1

M0

Format

0

0

0

0 - FSYNC & SCK Output

0

0

1

1 - Left/Right, 16-24 Bits

0

1

0

2 - Word Sync, 16-24 Bits

01

1

3 - Reserved

10

0

1

0

1

5 - LSB Justified, 16 Bits

1

1

0

6 - LSB Justified, 18 Bits

1

1

1

7 - MSB Last, 16-24 Bits