TDA7512F datasheet(21/45 Pages) STMICROELECTRONICS

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TDA7512F

Functional description

Doc ID 12668 Rev 2

21/45

tTIM < tCNT - tERR

tTIM = IF timer cycle time (sampling time)

tCNT = IF counter cycle time

tERR = discrimination window (controlled by the EW registers)

The IF counter is only started by inlock information from the PLL part. It is enabled by

software (IFENA).

4.5.10

Adjustment of the measurement sequence time

The precision of the measurements is adjustable by controlling the discrimination window.

This is adjustable by programming the control registers EW.

The measurement time per cycle is adjustable by setting the registers IFS.

4.5.11

Adjust of the frequency value

The center frequency of the discrimination window is adjustable by the control registers CF.

4.6

I2C bus interface

The TDA7512F supports the I2C bus protocol. This protocol defines any device that sends

data onto the bus as a transmitter, and the receiving device as the receiver. The device that

controls the transfer is a master and device being controlled is the slave. The master will

always initiate data transfer and provide the clock to transmit or receive operations.

4.6.1

Data transition

Data transition on the SDA line must only occur when the clock SCL is LOW. SDA transitions

while SCL is HIGH will be interpreted as START or STOP condition.

4.6.2

Start condition

A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a

stable HIGH level. This "START" condition must precede any command and initiate a data

transfer onto the bus.

The device continuously monitors the SDA and SCL lines for a valid START and will not

response to any command if this condition has not been met.

4.6.3

Stop condition

A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at

a stable HIGH level. This condition terminates the communication between the devices and

forces the bus-interface of the device into the initial condition.

4.6.4

Acknowledge

Indicates a successful data transfer. The transmitter will release the bus after sending 8 bits

of data. During the 9th clock cycle the receiver will pull the SDA line to LOW level to indicate

it receive the eight bits of data.

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