| 전자부품 데이터시트 검색엔진 |
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BAT30F3 데이터시트(PDF) 7 Page - STMicroelectronics |
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BAT30F3 데이터시트(HTML) 7 Page - STMicroelectronics |
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7 / 10 page ![]() BAT30F3 PCB recommendations Doc ID 16915 Rev 2 7/10 To optimize the natural self centering effect of CSP on the PCB, PCB pad positioning and size have to be properly designed (see Figure 10) Micro vias An alternative to routing on the top surface is to route out on buried layers. To achieve this, the pads are connected to the lower layers using micro vias. Only SSBU via technology is approved. Figure 10. Solder mask opening 370 µm 370 µm 100 µm 450 µm 180 µm 180 µm 255 µm Non solder mask defined Solder mask defined |
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