SPC560D40L1 datasheet(55/82 Pages) STMICROELECTRONICS

55 / 82 page

SPC560D30x, SPC560D40x

Electrical characteristics

Doc ID 16315 Rev 5

55/82

4.14

FMPLL electrical characteristics

The device provides a frequency-modulated phase-locked loop (FMPLL) module to

generate a fast system clock from the main oscillator driver.

VIH

SR P

Input high level CMOS

(Schmitt Trigger)

Oscillator bypass mode

0.65VDD

—VDD+0.4

VIL

SR P

Input low level CMOS

(Schmitt Trigger)

Oscillator bypass mode

−0.4

—

0.35VDD

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled

peripherals).

Table 37.

Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

Table 38.

FMPLL electrical characteristics

Symbol

Parameter

Conditions(1)

Value(2)

Unit

Min

Typ

Max

fPLLIN

SR — FMPLL reference clock(3)

—4

—

MHz

ΔPLLIN SR —

FMPLL reference clock duty

cycle(3)

—40

—

fPLLOUT CC D FMPLL output clock frequency

—

MHz

fVCO

(4)

CC P

VCO frequency without

frequency modulation

—256

—

512

MHz

VCO frequency with frequency

modulation

—245

—

533

fCPU

SR — System clock frequency

—

MHz

fFREE

CC P Free-running frequency

—

150

MHz

tLOCK

CC P FMPLL lock time

Stable oscillator (fPLLIN = 16 MHz)

—

100

µs

ΔtLTJIT CC — FMPLL long term jitter

fPLLIN = 16 MHz (resonator),

fPLLCLK at 48 MHz, 4000 cycles

—

IPLL

CC C FMPLL consumption

TA = 25 °C

—

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

All values need to be confirmed during device validation.

PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional

mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN.

Frequency modulation is considered ±4%.

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