STLC3055N_09 datasheet(16/34 Pages) STMICROELECTRONICS

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Application information

STLC3055N

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Application information

5.1

Layout recommendation

A properly designed PCB layout is a basic issue to guarantee a correct behavior and good

noise performances. Noise sources can be identified in not enough good grounds, not

enough low impedance supplies and parasitic coupling between PCB tracks and high

impedance pins of the device.

Particular care must be taken on the ground connection and in this case the star

configuration allows surely to avoid possible problems (see Figure 8 on page 20 and

Figure 9 on page 21).

The ground of the power supply (VPOS) has to be connected to the center of the star, let’s

call this point Supply GND. This point should show a resistance as low as possible, that

means it should be a ground plane.

In particular to avoid noise problems the layout should prevent any coupling between the

DC/DC converter components that are referred to PGND (CVPOS, CD, L) and analog pins

that are referred to AGND (ex: RD, IREF, RTH, RLIM, VF). AGND and BGND must be

shorter together. The GND connection of protection components have to be connected to

the Supply GDND.

As a first recommendation the components CV, L, D1, CVPOS, RSENSE should be kept as

close as possible to each other and isolated from the other components.

Additional improvements can be obtained:

●

decoupling the center of the star from the analog ground of STLC3055N using small

chokes.

●

adding a capacitor in the range of 100 nF between VPOS and AGND in order to filter

the switch frequency on VPOS.

STLC3055N 데이터시트(PDF) 16 Page - STMicroelectronics