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CXP83508/83512/83516, CXP83509/83513/83517

Chip select transfer mode

(SCK = output mode)

Chip select transfer mode

(SCK = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode

Note 1)

clock control register (CLC: 00FEh).

Note 2) CS, SCK, SI and SO indicates CS0, SCK0, SI0 and SO0, respectively.

Note 3) The load condition for the SCK output mode, SO output delay time is 50pF.

Note 4) The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer

capability to high.

Serial transfer (CH0)

Item

CS

↓ → SCK

delay time

CS

↑ → SCK

float delay time

CS

↓ → SO

delay time

CS

↓ → SO

float delay time

CS high level width

SCK cycle time

SCK high and low

level widths

SI input setup time

(for SCK

↑)

SI input hold time

(for SCK

↑)

SCK

↓ → SO

delay time

SCK0

SCK0

SO0

SO0

CS0

SCK0

SCK0

SI0

SI0

SO0

Input mode

Output mode

Input mode

Output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

ns

ns

ns

ns

ns

Symbol

Pin

Min.

2

16000/fc

8000/fc – 150

–

200

2

100

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

2

125

Max.

Unit

Conditions