Introduction

STiH205

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Doc ID 019040 Rev 3

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Introduction

The STiH205 offers current users of ST’s growing family of advanced decoding ICs

enhancements in performance and features, enabling operators to offer consumers new

multimedia-rich services and viewing experiences, including new 3DTV features. Faster

DDR3 memory is also supported, and the applications CPU benefits from an L2 cache. The

STiH205 keeps pace with the latest advanced security requirements of the main CA

vendors, and an integrated standby controller enables the STiH205 to target stringent low

power regulations.

Features

Benefits

ST40 applications CPU, with 32 KI and 32 KD

L1 caches and 256 Kbyte L2 cache.

High performance processing for applications and

middleware.

Integrated low power standby controller within its

own power island.

Secure hibernation to, and fast resume from, very

low power passive standby mode, targeting STB

standby power < 0.5 W.

Latest generation of ST's Delta video decoder,

coupled with a High Quality Video Display

Pipeline (HQVDP).

Decoding of advanced high-definition standards

(MPEG2, H264, VC-1, AVS) plus the performance

and flexibility for web-based content decoding such

impacting applications CPU performance.

Dual USB 2.0 hosts, eSATA, Ethernet MAC with

MII/RMII/TMII interfaces, PCI-e, SD-MMC/SDIO

interface.

Extensive high-speed connectivity for the widest

range of STB peripherals, such as Flash drives,

external HDDs, Ethernet, home network controllers

memory cards.

NOCS3.0, NSK2.0 and DVB-CSA3 ready.

Fully compliant with the latest advanced security

requirements of CA vendors.

23 mm x 23 mm package, smaller than other

STiH205/STiH207 family variants.

Ideal for space constrained form factors such as

dongles and plug based STBs and media players.