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MAX15021 데이터시트(PDF) 19 Page - Maxim Integrated Products

부품명 MAX15021
상세설명  Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability
PDF  24 Pages
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제조업체  MAXIM [Maxim Integrated Products]
홈페이지  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX15021 데이터시트(HTML) 19 Page - Maxim Integrated Products

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The locations of the zeros and poles should be such
that the phase margin peaks around fCO.
Set the ratios of fCO-to-fZ and fP-to-fCO equal to one anoth-
er, e.g., fCO = fP = 5 is a good number to get approximately
fZ
fCO
60° of phase margin at fCO. Whichever technique, it is
important to place the two zeros at or below the double
pole to avoid the conditional stability issue.
The following procedure is recommended:
1) Select a crossover frequency, fCO, at or below one-
tenth the switching frequency (fSW):
2) Calculate the LC double-pole frequency, fLC :
where COUT is the output capacitor of the regulator.
3) Select the feedback resistor, RF, in the range of
3.3k
Ω to 30kΩ.
4) Place the compensator’s first
zero at or below the output filter’s
double-pole, fLC , as follows:
5) The gain of the modulator (GainMOD)—comprised of
the regulator’s pulse-width modulator, LC filter,
feedback divider, and associated circuitry—at the
crossover frequency is:
The gain of the error amplifier (GainE/A) in midband fre-
quencies is:
The total loop gain is the product of the modulator gain
and the error amplifier gain at fCO should be equal to 1,
as follows:
GainMOD x GainE/A = 1
So:
Solving for CI:
6) For those situations where fLC < fCO < fESR < fSW/2,
as with low-ESR tantalum capacitors, the compen-
sator’s second pole (fP2) should be used to cancel
fESR. This provides additional phase margin. On the
system Bode plot, the loop gain maintains its
+20dB/decade slope up to 1/2 of the switching fre-
quency verses flattening out soon after the 0dB
crossover. Then set:
fP2 = fESR
If a ceramic capacitor is used, then the capacitor ESR
zero, fESR, is likely to be located even above one-half of
the switching frequency, that is fLC < fCO < fSW/2 <
fESR. In this case, the frequency of the second pole
(fP2) should be placed high enough not to significantly
erode the phase margin at the crossover frequency.
For example, fP2 can be set at 5 x fCO, so that its con-
tribution to phase loss at the crossover frequency fCO is
only about 11°:
fP2 = 5 x fCO
Once fP2 is known, calculate RI:
7) Place the second zero (fZ2) at 0.2 x fCO or at fLC,
whichever is lower, and calculate R1 using the fol-
lowing equation:
8) Place the third pole (fP3) at 1/2 the switching fre-
quency and calculate CCF from:
9) Calculate R2 as:
where VFB = 0.6V (typ).
R [k] R [k]
V
[V]
V
[V] V
[V]
21
FB
OUT_
FB
ΩΩ
=×
−
C[ F]
1
2
0.5 f
[MHz] R [k ]
CF
SW
F
n
=
××
×
()
πΩ
R[k ]
1
2
f
[kHz] C [ F]
1
Z2
I
Ω=
××
πμ
R[k ]
1
2
f
[kHz] C [ F]
I
P2
I
Ω=
××
πμ
C pF]
2
f
[kHz] L[ H] C
[ F]
4 R [k ]
I
CO
OUT
F
[
=
××
×
()
×
πμ
μ
Ω
4
1
(2
f
[kHz])
C
[ F] L[ H]
2
f
[kHz] C [ F] R [k ]
1
CO
2
OUT
CO
I
F
×
××
×
××
×
×
=
πμ
μ
π
p
Ω
Gain
2
f
[kHz] C [ F] R [k ]
E/A
CO
I
F
=×
×
×
πμ
Ω
Gain
4
1
(2
f
[MHz])
L[ H] C
[ F]
MOD
CO
2
OUT
=×
××
×
πμ
μ
C[ F]
1
2
R [k ] 0.5 f
[kHz]
F
FLC
μ
π
=
××
×
Ω
f
[MHz]
1
2
L[ H]
C
F]
LC
OUT
≈
××
πμ
μ
[
f
[kHz]
f
[kHz]
10
CO
SW
≤
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Tracking/Sequencing Capability
MAX15021
Maxim Integrated
19
f
1
2R
C
Z1
FF
=
××
π



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