WM7220

Preliminary Technical Data

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PTD, Rev 2.3, December 2011

6

6.

SLEEP Mode is enabled when the CLK input is below the CLK Sleep Frequency noted above. This is a power saving

mode. Normal operation resumes automatically when the CLK input is above the CLK Sleep Frequency. Note that the

VDD supply is still required in SLEEP mode.

AUDIO INTERFACE TIMING

Figure 1 Digital Microphone Interface Timing

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Digital Microphone Interface Timing

CLK cycle time

325

976

ns

CLK duty cycle

60:40

40:60

DAT enable from rising CLK edge (LRSEL = 1)

18

ns

DAT disable from falling CLK edge (LRSEL = 1)

16

ns

DAT enable from falling CLK edge (LRSEL = 0)

18

ns

DAT disable from rising CLK edge (LRSEL = 0)

16

ns

Notes:

1.

The DAT output is high-impedance when not outputting data; this enables the outputs of two microphones to be

connected together, with the data from one microphone interleaved with the data from the other. (The microphones

must be configured to transmit on opposite channels in this case.)

2.

In a typical configuration, the Left channel is transmitted following the rising CLK edge (LRSEL = 1). In this case, the

Left channel should be sampled by the receiving device on the falling CLK edge,

3.

Similarly, the Right channel is typically transmitted following the falling CLK edge (LRSEL = 0). In this case, the Right

channel should be sampled by the receiving device on the rising CLK edge.