 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
WM8948 데이터시트(PDF) 39 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8948 데이터시트(HTML) 39 Page - Wolfson Microelectronics plc |
|
|
39 / 189 page  Production Data WM8948 w PD, May 2011, Rev 4.1 39 Typical applications of the 5-band EQ include the selection of user-preferences for different music types, such as ‘rock’, ‘dance’ or ‘classical’ EQ profiles. Note that when the right channel 5BEQ filter is disabled the gains for each of the frequency bands must be set to 0dB. DYNAMIC RANGE CONTROL (DRC) DRC Signal Enhancement Block 3 (SE3) The Dynamic Range Control (DRC) forms the SE3 block. The DRC provides a range of compression, limiting and noise gate functions to support optimum configuration for recording or playback modes. The DRC is configured using the control fields in registers R29 to R35 - see “Dynamic Range Control”. SIGNAL ENHANCEMENT REGISTER CONTROLS The SE1 ‘enable’ bits are described in Table 13. Note that other control fields must also be determined and written to the WM8948 using WISCE™ or other tools. The registers described below only allow the sub-blocks of SE1 to be enabled or disabled. Note that it is not recommended to access these control fields unless appropriate values have been written to the associated bits in registers R65 to R98. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R65 (41h) SE1_LHPF_ CONFIG 1 SE1_LHPF_R_ ENA 0 SE1 Right channel low-pass / high- pass filter enable 0 = Disabled 1 = Enabled 0 SE1_LHPF_L_ ENA 0 SE1 Left channel low-pass / high- pass filter enable 0 = Disabled 1 = Enabled R68 (44h) SE1_3D_ CONFIG 1 SE1_3D_R_ENA 0 SE1 Right channel 3D stereo enhancement filter enable 0 = Disabled 1 = Enabled 0 SE1_3D_L_ENA 0 SE1 Left channel 3D stereo enhancement filter enable 0 = Disabled 1 = Enabled R71 (47h) SE1_NOTCH_ CONFIG 1 SE1_NOTCH_R _ENA 0 SE1 Right channel notch filters enable 0 = Disabled 1 = Enabled 0 SE1_NOTCH_L _ENA 0 SE1 Left channel notch filters enable 0 = Disabled 1 = Enabled R92 (5Ch) SE1_DF1_ CONFIG 1 SE1_DF1_R_ ENA 0 SE1 Right channel DF1 filter enable 0 = Disabled 1 = Enabled 0 SE1_DF1_L_ ENA 0 SE1 Left channel DF1 filter enable 0 = Disabled 1 = Enabled Table 13 Signal Enhancement Block 1 (SE1) |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
