WM8948ECSSLASHR datasheet(71/189 Pages) WOLFSON

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Production Data

WM8948

PD, May 2011, Rev 4.1

In Slave mode, LRCLK and BCLK are configured as inputs, and the data timing is controlled by an

external master.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

Clock Gen

control

3:1

BCLK_DIV [2:0]

011

BCLK Frequency (Master mode)

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 4

011 = SYSCLK / 8

100 = SYSCLK / 16

101 = SYSCLK / 32

110 = reserved

111 = reserved

MSTR

Digital Audio Interface Mode select

0 = Slave mode

1 = Master mode

Table 44 Digital Audio Interface Control

AUDIO DATA FORMATS

Three basic audio data formats are supported:

•

Left justified

•

I2S

•

DSP mode

All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the

Electrical Characteristic section for timing information.

PCM operation is supported using the DSP mode.

The WM8948 can control the channel selection between the ADCs and the ADCDAT pin. Similarly,

the channel selection between the DACDAT pin and the DACs is selectable. Digital inversion of the

ADC or DAC data is also possible.

The register bits controlling audio data format and channel configuration are described in Table 45.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (04h)

Audio

Interface

ADCR_SRC

Right Digital Audio interface source

0 = Left ADC data is output on right

channel

1 = Right ADC data is output on

right channel

ADCL_SRC

Left Digital Audio interface source

0 = Left ADC data is output on left

channel

1 = Right ADC data is output on left

channel

DACR_SRC

Right DAC Data Source Select

0 = Right DAC outputs left interface

data

1 = Right DAC outputs right

interface data

DACL_SRC

Left DAC Data Source Select

0 = Left DAC outputs left interface

data

1 = Left DAC outputs right interface

data

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