WM8961 datasheet(73/116 Pages) WOLFSON

73 / 116 page

WM8961

Pre-Production

PP, August 2009, Rev 3.1

SYSCLK

SYSCLK is derived directly from MCLK. It is either MCLK or MCLK/2. The CLK_SYS_ENA enables

the internal SYSCLK. The CLK_DSP_ENA allows the clock to the DSP, ADC and DAC to be disabled

(for power reduction) while peripheral functions continue to be clocked by SYSCLK.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (04h)

Clocking1

MCLKDIV

SYSCLK configuration.

0 : SYSCLK = MCLK/1

1 : SYSCLK = MCLK/2

R8 (08h)

Clocking2

CLK_SYS_ENA

Enable system clock. Power saving feature to gate SYSTEM

clock. When this bit is enabled, an MCLK must be provided to

allow access to the control interface.

CLK_DSP_ENA

DSP clock enable. Power saving feature to gate clock to DSP

while allowing auxiliary functions to run.

Table 53 SYSCLK Configuration

ADC AND DAC CLOCKING AND SAMPLE RATES

The ADCDIV and DACDIV bits determine the ADC and DAC operating clock. The output of ADCDIV

should be configured to output a clock of 256fs. The 256fs output of ADCDIV is further divided such

that the ADC operates at 128fs.

The DAC should be configured to run at a clock frequency as close as possible to 3MHz. This

requires setting the DACDIV divider to output a clock of at least 64fs.

ADC Example

SYSCLK=12.288 MHz, and fs=24 kHz. Then ADCDIV should be set to 010 (SYSCLK/2)..

This defines the output of the ADCDIV as 256fs = (12.288 MHz /2) = 6.144 MHz.

This 6.144 MHz is further divided by 2 (ADC runs at 128fs) to drive the ADC. Further examples are

given in Table 55.

DAC Example

SYSCLK=11.2896 MHz and fs=44.1 kHz. Then DACDIV should be set to =100.

This defines the output of the DACDIV as 64fs = (11.2896 MHz /4) = 2.8224 MHz

Further examples are given in Table 55 (when both ADC and DAC used) and Table 56 (DAC only

use).

In master mode the output BCLK is controlled by BCLKDIV, and the LRC is controlled by

LRCLK_RATE. These are shown in Table 54 ADC, DAC and Master Mode BCLK and LRC Control.

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