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WM8224 데이터시트(PDF) 21 Page - Wolfson Microelectronics plc

부품명 WM8224
상세설명  60MSPS 3-Channel AFE with Multiple Device Operation and Programmable Automatic Black Level Calibration
PDF  50 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
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WM8224 데이터시트(HTML) 21 Page - Wolfson Microelectronics plc

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WM8224
Production Data
w
PD, Rev 4.1, June 2012
21
CDS/NON-CDS PROCESSING
For CCD type input signals, containing a fixed reference/reset level, the signal may be processed
using Correlated Double Sampling (CDS), which will remove pixel-by-pixel common mode noise. With
CDS processing the input waveform is sampled at two different points in time for each pixel, once
during the reference/reset level and once during the video level. To sample using CDS, register bit
CDS must be set to 1 (default). This causes the signal reference to come from the video reference
level as shown in Figure 16.
The video sample is always taken on the falling edge of the input VSMP signal (VS). In CDS-mode
the reset level is sampled on the falling edge of the RSMP input signal (RS).
For input signals that do not contain a reference/reset level (e.g. CIS sensor signals), non-CDS
processing is used (CDS=0). In this case, the video level is processed with respect to the voltage on
pin VRLC/VBIAS. The VRLC/VBIAS voltage is sampled at the same time as VSMP samples the
video level in this mode. Note that if the ac coupling capacitor (CIN) is used in non-CDS mode
(CDS=0), then to minimise code drift, line clamping should be used and internal input voltage buffers
enabled using the FOL_EN register bit.
Alternatively, if the input signal contains a stable
reference/reset level then pixel clamping should be used, and the voltage buffers need not be
enabled.
Figure 16 CDS/non-CDS Input Configuration
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by a 9-bit PGA. The gain and offset for each
channel are independently programmable by writing to control bits DAC[7:0] and PGA[8:0].
The gain characteristic of the WM8224 PGA is shown in Figure 17. Figure 18 shows the maximum
device input voltage that can be gained up to match the ADC full-scale input range (default=2V).



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