WM8985GEFL datasheet(21/121 Pages) WOLFSON

부품명	WM8985GEFL

상세설명	Multimedia CODEC with Class D Headphone and Line Out

PDF	121 Pages

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제조업체	WOLFSON [Wolfson Microelectronics plc]

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Production Data

WM8985

PD, Rev 4.6, July 2009

INTERNAL POWER ON RESET CIRCUIT

Figure 7 Internal Power on Reset Circuit Schematic

The WM8985 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used to

reset the digital logic into a default state after power up. The POR circuit is powered from AVDD1

and monitors DCVDD. It asserts PORB low if AVDD1 or DCVDD is below a minimum threshold.

Figure 8 Typical Power up Sequence where AVDD1 is Powered before DCVDD

Figure 8 shows a typical power-up sequence where AVDD1 comes up first. When AVDD1 goes

above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is

asserted low and the chip is held in reset. In this condition, all writes to the control interface are

ignored. Now AVDD1 is at full supply level. Next DCVDD rises to Vpord_on and PORB is released high

and all registers are in their default state and writes to the control interface may take place.

On power down, where AVDD1 falls first, PORB is asserted low whenever AVDD1 drops below the

minimum threshold Vpora_off.

WM8985GEFL 데이터시트(PDF) 21 Page - Wolfson Microelectronics plc