RT7250B datasheet(13/14 Pages) RICHTEK

13 / 14 page

RT7250A/B

DS7250A/B-01 May 2012

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Figure 3. Derating Curve of Maximum Power Dissipation

Layout Consideration

Follow the PCB layout guidelines for optimal performance

of the RT7250A/B

Keep the traces of the main current paths as short and

wide as possible.

Put the input capacitor as close as possible to the device

pins (VIN and GND).

SW node is with high frequency voltage swing and

should be kept at small area. Keep sensitive

components away from the SW node to prevent stray

capacitive noise pickup.

Place the feedback components to the FB pin as close

as possible.

The GND and Exposed Pad should be connected to a

strong ground plane for heat sinking and noise protection.

Checking Transient Response

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, VOUT immediately shifts by an amount

equal to

ΔILOAD (ESR) also begins to charge or discharge

COUT generating a feedback error signal for the regulator

to return VOUT to its steady-state value. During this

recovery time, VOUT can be monitored for overshoot or

ringing that would indicate a stability problem.

Thermal Considerations

For continuous operation, do not exceed the maximum

operation junction temperature 125

°C. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

Where TJ(MAX) is the maximum operation junction

temperature, TA is the ambient temperature and the

θJAis

the junction to ambient thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

θJA, is layout dependent. For

SOP-8 (Exposed Pad) packages, the thermal resistance,

θJA, is 75°C/W on a standard JEDEC 51-7 four-layer

thermal test board. The maximum power dissipation at TA

= 25

°C can be calculated by the following formula :

PD(MAX) = (125

°C − 25°C) / (75°C/W) = 1.333W for

SOP-8 (Exposed Pad) package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curve in Figure 3 allows the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

VOUT

COUT

CIN

CBOOT

GND

Input capacitor must

be placed as close

to the IC as possible.

SW should be connected to

inductor by wide and short trace.

Keep sensitive components

away from this trace.

The resistor divider must be

connected as close to the

device as possible.

VIN

BOOT

GND

PGOOD

GND

Figure 4. PCB Layout Guide

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

100

125

Ambient Temperature (°C)

Four-Layer PCB

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