SAM4SD32C datasheet(39/67 Pages) ATMEL

39 / 67 page

11100BS–ATARM–31-Jul-12

SAM4S Series [Preliminary]

Setting the GPNVM Bit 2 selects bank 1, clearing it selects the boot from bank 0. Asserting

ERASE clears the GPNVM Bit 2 and thus selects the boot from bank 0 by default.

9.2

External Memories

The SAM4S features one External Bus Interface to provide an interface to a wide range of exter-

nal memories and to any parallel peripheral.

9.2.1

Static Memory Controller

• 16-Mbyte Address Space per Chip Select

• 8- bit Data Bus

• Word, Halfword, Byte Transfers

• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select

• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select

• Programmable Data Float Time per Chip Select

• External Wait Request

• Automatic Switch to Slow Clock Mode

• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes

• NAND Flash additional logic supporting NAND Flash with Multiplexed Data/Address buses

• Hardware Configurable number of chip selects from 1 to 4

• Programmable timing on a per chip select basis

10. System Controller

The System Controller is a set of peripherals which allows handling of key elements of the sys-

tem, such as power, resets, clocks, time, interrupts, watchdog, etc...

See the system controller block diagram in Figure 10-1 on page 40.

SAM4SD32C 데이터시트(PDF) 39 Page - ATMEL Corporation