AD1816A

–17–

REV. A

SERIAL INTERFACES

I

The two I

Figure 9 shows the right-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the rising

edge of the BCLK. The MSB is delayed 16-bit clock periods from an LRCLK transition, so that when there are 64 BCLK periods

per LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition.

14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

15

LRCLK

BCLK

SDATA

15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

LEFT CHANNEL

RIGHT CHANNEL

Figure 9. Serial Interface Right-Justified Mode

Figure 10 shows the I

edge of BCLK. The MSB is left-justified to an LRCLK transition, but with a single BCLK period delay.

LRCLK

BCLK

SDATA

15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

LEFT CHANNEL

RIGHT CHANNEL

14 13 12 11 10 9

8

7

6

5432

10

15

Figure 11 shows the left-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the rising

edge of BCLK. The MSB is left-justified to an LRCLK transition, with no MSB delay.

LRCLK

BCLK

SDATA

15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

LEFT CHANNEL

RIGHT CHANNEL

14 13 12 11 10 987

6

54321

0

15

Figure 11. Serial Interface Left-Justified Mode

Bidirectional DSP Serial Interface

The AD1816A SoundPort Controller transmits and receives both data and control/status information through its DSP serial interface

port (SPORT). The AD1816A is always the bus master and supplies the frame sync and the serial clock. The AD1816A has four

pins assigned to the SPORT: SDI, SDO, SDFS and SCLK. The SPORT has two operating modes: monitor and intercept. The

SPORT always monitors the various data streams being processed by the AD1816A. In intercept mode, any of the digital data

streams can be manipulated by the DSP before reaching the final ADC or DAC stages.

The SDI and SDO pins handle the serial data input and output of the AD1816A. Communication in and out of the AD1816A requires

that bits of data be transmitted after a rising edge of SCLK and sampled on the falling edge of SCLK. The SCLK frequency is

always 11 MHz (or 1/3 or XTALI).

DSP Serial Port Interface time slots are mapped as shown in Table I.