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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD1843JS 데이터시트(PDF) 27 Page - Analog Devices |
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AD1843JS 데이터시트(HTML) 27 Page - Analog Devices |
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27 / 64 page  AD1843 REV. 0 –27– 8 9 GNDD VDD S E L E C T O R 2 LEFT RIGHT LEFT RIGHT 3 VCC ADC µ/A LAW D I G I T A L I N T E R F A C E CONTROL AND STATUS REGISTERS CRA0, CRA1, CRA25, CRA26, CRA27, CRA28 RESET PWRDWN ∑ ∑ MUTE ATTN ∑ ∑ MUTE ∑ ∑ ∑ ∑ FIFO S E L E C T O R µ/A LAW SCLK SDFS SDI SDO BM CS TSO TSI XCTL [1:0] PDMNFT CLOCK GENERATION CLKOUT XTALI XTALO SYNC3 SYNC2 SYNC1 CONV3 CONV2 CONV1 BIT3 BIT2 BIT1 CRA15, CRA16, CRA17, CRA18, CRA19, CRA20, CRA21, CRA22, CRA23, CRA24 AD1843 CRAX = CONTROL REGISTER ADDRESS “X” CRA25 CRA25 CRA25 CRA25 CRA12 CRA11 ATTN MUTE CRA13 ATTN MUTE CRA14 CRA26 CRA26 DAC1 DAC2 CRA26 µ/A LAW FIFO ATTN Address Register Description 16 Clock Generator 1 Control—Mode 17 Clock Generator 1 Control—Sample Rate 18 Clock Generator 1 Control—Sample Phase Shift 19 Clock Generator 2 Control—Mode 20 Clock Generator 2 Control—Sample Rate 21 Clock Generator 2 Control—Sample Phase Shift 22 Clock Generator 3 Control—Mode 23 Clock Generator 3 Control—Sample Rate 24 Clock Generator 3 Control—Sample Phase Shift 25 Codec Configuration—Digital Filter and Mode Select 26 Codec Configuration—Serial Interface 27 Codec Configuration—Channel Power Down 28 Codec Configuration—Fundamental Settings 29 Reserved for Future Expansion 30 Reserved for Future Expansion 31 Reserved for Future Expansion Figure 13. AD1843 Control Registers Associated with Block Diagram |
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