AD5122/AD5142

Data Sheet

Rev. 0 | Page 12 of 32

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NOTES

1. INTERNALLY CONNECT THE

AD5122/

AD5142

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

1

GND

2

A1

3

W1

4

B1

9

Figure 6. 16-Lead LFCSP Pin Configuration

Table 8. 16-Lead LFCSP Pin Function Descriptions

Pin No.

Mnemonic

Description

1

GND

Ground Pin, Logic Ground Reference.

2

A1

Terminal A of RDAC1. V

3

W1

Wiper Terminal of RDAC1. V

4

B1

Terminal B of RDAC1. V

5

V

SS

Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

6

A2

Terminal A of RDAC2. V

7

W2

Wiper Terminal of RDAC2. V

8

B2

Terminal B of RDAC2. V

9

V

DD

Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

10

V

LOGIC

Logic Power Supply; 1.8 V to V

11

SCLK

Serial Clock Line. Data is clocked in at the logic low transition.

12

SDI

Serial Data Input.

13

SDO

Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor.

14

SYNC

Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register.

15

INDEP

Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from its associated

memory location. If INDEP is enabled, it cannot be disabled by software.

16

RESET

Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is

EPAD

Internally Connect the Exposed Pad to V