AD261

–6–

REV. 0

BUFFER

DELAY LINE

BUFFER

14ns

100

5pF

OUTPUT

CAPACITANCE

TOTAL DELAY =

t

PD

t

t

ff

t

0.5ns – NO LOAD

= 5.5ns INTO 50pF

5pF

INPUT

CAPACITANCE

EFFECTIVE

CIRCUIT

MODEL

37%

63%

OUTPUT

INPUT

POSITIVE GOING

INPUT THRESHOLD

NEGATIVE GOING

INPUT THRESHOLD

HYSTERESIS

PROPAGATION DELAY

t

Figure 2. Typical Timing and Delay Models

22-Pin Plastic DIP

(ND-22A)

BOTTOM

VIEW

SYSTEM

FIELD

0.738* (18.75)

0.650 (16.51)

0.250

(6.35)

0.050

(1.27)

PIN 1

0.075 (1.91)

SIDE VIEW

22

1

8

15

1.500 (38.1) MAX

0.050 (1.27)

0.160 (4.06)

0.140 (3.56)

0.020

0.010

(0.508

0.254)

16 PLACES

0.100

(2.54)

0.550 (13.97)

MAX

0.440

(11.18)

MAX

END VIEW

0.350

(8.89)

*CREEPAGE PATH (SUBTRACT APPROXIMATELY

0.079 (2mm) FOR SOLDER PAD RADII ON PC BOARD.

THIS SPACING SUPPORTS THE INTRINSICALLY SAFE

RATING OF 750V.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Logic information is sent across the barrier as “set-hi/set-lo”

data that is derived from logic level transitions of the input. At

power-up or after a fault condition, an output might not repre-

sent the state of the respective channel input to the isolator. An

internal circuit operates in the background which interrogates

all inputs about every 5

µs and in the absence of logic transi-

tions, sends appropriate “set-hi” or “set-lo” data across the

barrier.

Recovery time from a fault condition or at power-up is thus

between 5

µs and 10 µs.

DRIVER

DATA

RECEIVER

OUTPUT

BUFFER

GATED

TRANSPARENT

LATCH

SCHMITT

TRIGGER

BUFFER

CONTINUOUS

UPDATE CIRCUIT

3.5kV

ISOLATION

BARRIER

DATA IN

ENABLE

ENABLE

OUT

DQ

G

Figure 1. Simplified Block Diagram