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DA6180B.002

5 May, 2011

MAS6180 SAMPLES IN PDIP-20 PACKAGE

Top Marking Definitions:

YYWW = Year Week

XXXXX = Lot Number

zz =Sample Version

1

VDD 2

3

QOP 4

QOM

5

6

QI

7

AGC 8

9

OUT 10

20 VSS

19

18 RFIM

17 RFIP

16

15

14 PDN

13 AON

12 DEC

11

PIN DESCRIPTION

Pin Name

Pin

Type

Function

Note

1

NC

VDD

2

P

Positive Power Supply

3

NC

QOP

4

AO

Positive Quartz Filter Output for Crystal

QOM

5

AO

Negative Quartz Filter Output for External

Compensation Capacitor or Second Crystal

1

6

NC

2

QI

7

AI

Quartz Filter Input for Crystal and External

Compensation Capacitor

AGC

8

AO

AGC Capacitor

9

NC

OUT

10

DO

Receiver Output

3

11

NC

DEC

12

AO

Demodulator Capacitor

AON

13

DI

AGC On Control

4

PDN

14

DI

Power Down Input

5

15

NC

16

NC

RFIP

17

AI

Positive Receiver Input

6

RFIM

18

AI

Negative Receiver Input

6

19

NC

VSS

20

G

Power Supply Ground

A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected

Notes:

1) External crystal compensation capacitor pin QOM is connected only in MAS6180B5 version. It is left

unconnected in MAS6180B1 version which has internal compensation capacitor.

2) Pin 6 between QOM and QI must be connected to VSS to eliminate DIL package lead frame parasitic

capacitances disturbing the crystal filter performance. All other NC (Not Connected) type pins are also

recommended to be connected to VSS to minimize noise coupling.

3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)

-

-

at power down the output is pulled to VSS (pull down switch)

4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)

-

Internal pull-up with current < 1 µA which is switched off at power down

5) PDN = VSS means receiver on; PDN = VDD means receiver off

-

Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up

(PDN=VSS) i.e. at the falling edge of PDN signal.

6) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD