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AD5313 데이터시트(PDF) 14 Page - Analog Devices

부품명 AD5313
상세설명  2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
PDF  20 Pages
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AD5313 데이터시트(HTML) 14 Page - Analog Devices

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REV. F
–14–
AD5305/AD5315/AD5325
READ OPERATION
When reading data back from the AD5305/AD5315/AD5325
DACs, the user begins with an address byte (R/
W = 0), after which
the DAC will acknowledge that it is prepared to receive data by
pulling SDA low. This address byte is usually followed by the
pointer byte, which is also acknowledged by the DAC. Following
this, there is a repeated start condition by the master and the
address is resent with R/
W = 1. This is acknowledged by the DAC
indicating that it is prepared to transmit data. Two bytes of data
are then read from the DAC, as shown in Figure 9. A STOP
condition follows.
However, if the master sends an ACK and continues clocking
SCL (no STOP is sent), the DAC will retransmit the same two
bytes of data on SDA. This allows continuous readback of data
from the selected DAC register.
Alternatively, the user may send a START followed by the address
with R/
W = 1. In this case, the previously loaded pointer settings
are used and readback of data can commence immediately.
DATA BYTE
LEAST SIGNIFICANT DATA BYTE
00
0
1
1
A0
R/
W
XX
LSB
ACK
BY
AD53x5
SCL
SDA
START
COND
BY
MASTER
ACK
BY
AD53x5
MSB
SCL
SDA
00
0
1
1
0
A0
R/
W
MSB
LSB
ACK
BY
MASTER
REPEATED
START
COND
BY
MASTER
ACK
BY
AD53x5
ADDRESS BYTE
SCL
SDA
MSB
LSB
NO
ACK
BY
MASTER
STOP
COND
BY
MASTER
POINTER BYTE
ADDRESS BYTE
0
NOTE: DATA BYTES ARE THE SAME AS THOSE IN THE WRITE SEQUENCE EXCEPT THAT DON’T CARES ARE READ BACK AS 0s.
Figure 9. Readback Sequence



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