AD565A/AD566A

AD566AS

AD566AT

Model

Min

Typ

Max

Min

Typ

Max

Units

DATA INPUTS

TTL or 5 Volt CMOS

Input Voltage

Bit ON Logic “1”

+2.0

+5.5

+2.0

+5.5

V

Bit OFF Logic “0”

0

+0.8

0

+0.8

V

Logic Current (Each Bit)

Bit ON Logic “1”

+120

+300

+120

+300

µA

Bit OFF Logic “0”

+35

+100

+35

+100

µA

RESOLUTION

12

12

Bits

OUTPUT

Current

Unipolar (All Bits On)

–1.6

–2.0

–2.4

–1.6

–2.0

–2.4

mA

Bipolar (All Bits On or Off)

0.8

± 1.0

1.2

0.8

± 1.0

1.2

mA

Resistance (Exclusive of Span Resistors)

6

8

10

6

8

10

k

Ω

Offset

Unipolar (Adjustable to Zero per Figure 3)

0.01

0.05

0.01

0.05

% of F.S. Range

Bipolar (Figure 4, R1 and R2 = 50

Ω Fixed)

0.05

0.15

0.05

0.1

% of F.S. Range

Capacitance

25

25

pF

Compliance Voltage

–1.5

+10

–1.5

+10

V

ACCURACY (Error Relative to

Full Scale) +25

°C

± 1/4

1/2

± 1/8

1/4

LSB

(0.006)

(0.012)

(0.003)

(0.006)

% of F.S. Range

± 1/2

3/4

± 1/4

1/2

LSB

(0.012)

(0.018)

(0.006)

(0.012)

% of F.S. Range

DIFFERENTIAL NONLINEARITY

+25

°C

± 1/2

3/4

± 1/4

1/2

LSB

MONOTONICITY GUARANTEED

MONOTONICITY GUARANTEED

TEMPERATURE COEFFICIENTS

Unipolar Zero

1

2

1

2

ppm/

°C

Bipolar Zero

5

10

5

10

ppm/

°C

Gain (Full Scale)

7

10

3

5

ppm/

°C

Differential Nonlinearity

2

2

ppm/

°C

SETTLING TIME TO 1/2 LSB

All Bits ON-to-OFF or OFF-to-ON (Figure 8)

250

350

250

350

ns

FULL-SCALE TRANSITION

10% to 90% Delay plus Rise Time

15

30

15

30

ns

90% to 10% Delay plus Fall Time

30

50

30

50

ns

POWER REQUIREMENTS

–12

–18

–12

–18

mA

POWER SUPPLY GAIN SENSITIVITY

2

15

25

15

25

ppm of F.S./%

PROGRAMMABLE OUTPUT RANGES

(see Figures 3, 4, 5)

0 to +5

0 to +5

V

–2.5 to +2.5

–2.5 to +2.5

V

0 to +10

0 to +10

V

–5 to +5

–5 to +5

V

–10 to +10

–10 to +10

V

EXTERNAL ADJUSTMENTS

Gain Error with Fixed 50

Ω

Resistor for R2 (Figure 3)

± 0.1

0.25

± 0.1

0.25

% of F.S. Range

Bipolar Zero Error with Fixed

50

Ω Resistor for R1 (Figure 4)

± 0.05

0.15

± 0.05

0.1

% of F.S. Range

Gain Adjustment Range (Figure 3)

± 0.25

± 0.25

% of F.S. Range

Bipolar Zero Adjustment Range

± 0.15

± 0.15

% of F.S. Range

REFERENCE INPUT

Input Impedance

15

20

25

15

20

25

k

Ω

POWER DISSIPATION

180

300

180

300

mW

MULTIPLYING MODE PERFORMANCE (All Models)

Quadrants

Two (2): Bipolar Operation at Digital Input Only

Reference Voltage

+1 V to +10 V, Unipolar

Accuracy

10 Bits (

±0.05% of Reduced F.S.) for 1 V dc Reference Voltage

Reference Feedthrough (Unipolar Mode,

All Bits OFF, and 1 V to +10 V [p-p], Sine Wave

Frequency for l/2 LSB [p-p] Feedthrough)

40 kHz typ

Output Slew Rate 10%–90%

5 mA/

µs

90%–10%

1 mA/

µs

Output Settling Time (All Bits ON and a 0 V–10 V

Step Change in Reference Voltage)

1.5

µs to 0.01% F.S.

CONTROL AMPLIFIER

Full Power Bandwidth

300 kHz

Small-Signal Closed-Loop Bandwidth

1.8 MHz

NOTES

Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max

specifications are guaranteed, although only those shown in boldface are tested on all production units.

Specification subject to change without notice.

–5–

REV. D