AD6411

–7–

REV. 0

Transmit

DECT

Channel

A Counter

M Counter

Frequency/MHz

9

1

34

1881.792

8

2

34

1883.520

7

3

34

1885.248

6

4

34

1886.976

5

5

34

1888.704

4

6

34

1890.432

3

7

34

1892.160

2

8

34

1893.888

1

9

34

1893.888

0

10

34

1897.344

The A Counter range is 0–31, allowing the AD6411 to be used

in the extended DECT bands, up to the following maximum

frequency:

A Counter

M Counter

Frequency/MHz

31

34

1933.632

Receive (Local Oscillator Frequency)

Main values are shown for a 110.592 MHz IF frequency. Values

in parentheses are for the 112.32 MHz.

DECT

Channel

A Counter

M Counter

Frequency/MHz

9

1 (0)

32

1771.200 (1769.472)

8

2 (1)

32

1772.928 (1771.200)

7

3 (2)

32

1774.656 (1772.928)

6

4 (3)

32

1776.384 (1774.656)

5

5 (4)

32

1778.112 (1776.384)

4

6 (5)

32

1779.840 (1778.112)

3

7 (6)

32

1781.568 (1779.840)

2

8 (7)

32

1783.296 (1781.568)

1

9 (8)

32

1785.024 (1783.296)

0

10 (9)

32

1786.752 (1785.024)

Serial Interface

The IC operating modes can be controlled via the 3-wire

serial interface or via the three external control lines provided

(TX_ENAB, RX_ENAB, SYN_ENAB). The three external

control lines allow mode control of the IC if the baseband con-

troller cannot access the serial interface between slots. In either

case the 3-wire serial interface is used to program the channel

number. Detailed below is the register setup and the serial

interface operation.

The serial interface consists of a 16-bit shift register and two

registers for configuration of the IC and mode control. This

allows mode control of the IC with a single 16-bit write. DATA

is the serial data input (data MSB first), CLK is the shift regis-

ter clock (positive edge trigger), EN (positive edge trigger) is the

serial interface enable. All internal register values are retained

when sections of the IC are powered down. Figure 3 shows the

timing diagram for the serial interface.

EN

CLK

DATA

MSB

LSB

Figure 3. Serial Interface Timing Diagram

Parameter

Symbol

Typ

Unit

Maximum Serial Clock Frequency

f_clk

13.824

MHz

Serial Data Set Up Time

t_dst

8

ns

Serial Data Hold Time

t_dhd

8

ns

Enable Set Up to Clock High

t_hen

10

ns

Clock Low to Enable Low

t_den

5

ns

The Least Significant Bit of the serial control word selects either

the “one-time setup” register or the operating mode register,

with the remaining 15 bits as data. Table II below details the

internal IC register mapping.

Table II. Register Mapping

Address (D0)

Function

Comments

0

One-Time IC Setup

See Table III

1

IC Operating Mode

See Table IV

AD6411 INITIAL SETUP

On power-up the state of the IC is not defined. A one-time setup

register must be loaded through the serial interface port, and is

selected when the LSB of the serial word is 0. After this one-

time setup, a single serial word controls operation of the IC.

Table III. One-Time IC Setup Register

D15

D14

D13

D12

D11

D10

D9

D8

X

RSB

TSB

SSB

RXM1 RXM0 TXM

BSWS

D7

D6

D5

D4

D3

D2

D1

D0

CF0

CT1

CT0

DSD

SFM

PDS

RD

0