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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD7002AS 데이터시트(PDF) 6 Page - Analog Devices |
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AD7002AS 데이터시트(HTML) 6 Page - Analog Devices |
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6 / 16 page  AD7002 –6– REV. B INPUT CLOCK TIMING1 Limit at Parameter TA = –40 C to +85 C Units Description t1 76 ns min CLK1, CLK2, AUX CLK Cycle Time t2 30 ns min CLK1, CLK2, AUX CLK High Time t3 30 ns min CLK1, CLK2, AUX CLK Low Time TRANSMIT SECTION TIMING Limit at Parameter TA = –40 C to +85 C Units Description t4 10 ns min Tx SLEEP Hold Time t5 20 ns min Tx SLEEP Setup Time t6 24 t1 ns min Tx CLK Active After CLK1 Rising Edge Following 24 t1 + 80 ns max Tx SLEEP Low t7 48 t1 ns Tx CLK Cycle Time t8 24 t1 ns Tx CLK High Time t9 24 t1 ns Tx CLK Low Time t10 0 ns min Propagation Delay from CLK1 to Tx CLK 100 ns max 30 ns max t11 30 ns max Data Setup Time t12 10 ns min Data Hold Time t13 0 ns min Tx CLK to Tx SLEEP Asserted for Last Tx CLK Cycle 2 23 t1 ns max t14 10 ns typ Digital Output Rise Time 3 t15 10 ns typ Digital Output Fall Time 3 AUXILIARY DAC TIMING Limit at Parameter TA = –40 C to +85 C Units Description t16 10 ns min AUX DATA Setup Time t17 10 ns min AUX DATA Hold Time t18 25 ns min AUX LATCH to SCLK Falling Edge Setup Time t19 20 ns min AUX LATCH to SCLK Falling Edge Hold Time t20 50 ns max AUX LATCH High to AUX FLAG Valid Delay t21 10 ns typ Digital Output Rise Time t22 10 ns typ Digital Output Fall Time NOTES 1Sample tested at +25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2t 13 specifies a window, that Tx SLEEP should be asserted for the current Tx CLK to be the last prior to entering SLEEP mode. 3Digital output rise and fall times specify the time required for the output to go between 10% and 90% of 5 V. Specifications subject to change without notice. (AVDD = +5 V 10%; DVDD = +5 V 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted) (AVDD = +5 V 10%; DVDD = +5 V 10%; AGND = DGND = 0 V, fCLK1 = fCLK2 = 13 MHz; TA = TMIN to TMAX, unless otherwise noted) CLK1, CLK2, AUX CLK t 1 t 2 t 3 Figure 1. Clock Timing TO OUTPUT PIN +2.1V I OL 1.6mA I OH 200 µA C L 15pF Figure 2. Load Circuit for Timing Specifications (AVDD = +5 V 10%; DVDD = +5 V 10%; AGND = DGND = 0 V, fAUX CLK = 13 MHz; TA = TMIN to TMAX, unless otherwise noted) |
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